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MC74VHC373 Octal D-Type Latch with 3-State Output
The MC74VHC373 is an advanced high speed CMOS octal latch with 3-state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features http://onsemi.com MARKING DIAGRAMS
20
20 1
SOIC-20 WIDE DW SUFFIX CASE 751D 1
VHC373 AWLYYWW
* * * * * * * * * * * *
High Speed: tPD = 5.0 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.9 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 186 FETs or 46.5 Equivalent Gates Pb-Free Packages are Available*
20 TSSOP-20 DT SUFFIX CASE 948E 1 20
20 1
20 1
VHC 373 ALYW
SOEIAJ-20 M SUFFIX CASE 967 1 A WL, L YY, Y WW, W
74VHC373 AWLYYWW
= Assembly Location = Wafer Lot = Year = Work Week
PIN ASSIGNMENT
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
January, 2005 - Rev. 6
Publication Order Number: MC74VHC373/D
MC74VHC373
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
FUNCTION TABLE
INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L No Change Z
LE OE
11 1
Figure 1. Logic Diagram MAXIMUM RATINGS
Symbol VCC Vin Vout IIK IOK Iout ICC PD Tstg DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package Parameter Value - 0.5 to + 7.0 - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 20 20 25 75 500 450 - 65 to + 150 Unit V V V mA mA mA mA mW _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Vout TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Input Rise and Fall Time VCC = 3.3 V VCC = 5.0 V Parameter Min 2.0 0 0 - 40 0 0 Max 5.5 5.5 VCC + 85 100 20 Unit V V V _C ns/V
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MC74VHC373
DC ELECTRICAL CHARACTERISTICS
VCC V 2.0 3.0 to 5.5 2.0 3.0 to 5.5 Vin = VIH or VIL IOH = - 50 mA Vin = VIH or VIL IOH = - 4 mA IOH = - 8 mA VOL Maximum Low-Level Output Voltage Vin = VIH or VIL IOL = 50 mA Vin = VIH or VIL IOL = 4 mA IOL = 8 mA Iin IOZ Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current Vin = 5.5 V or GND Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 0 to 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 0.25 2.0 3.0 4.5 TA = 25C Min 1.50 VCC x 0.7 0.50 VCC x 0.3 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 2.5 mA mA V Typ Max TA = - 40 to 85C Min 1.50 VCC x 0.7 0.50 VCC x 0.3 Max Unit V
Symbol VIH
Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage
Test Conditions
VIL
V
VOH
V
ICC
5.5
4.0
40.0
mA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25C Symbol tPLH, tPHL Parameter Maximum Propagation Delay, D to Q Test Conditions VCC = 3.3 0.3 V VCC = 5.0 0.5 V tPLH, tPHL Maximum Propagation Delay, LE to Q VCC = 3.3 0.3 V VCC = 5.0 0.5 V tPZL, tPZH Output Enable Time, OE to Q VCC = 3.3 0.3 V RL = 1 kW VCC = 5.0 0.5 V RL = 1 kW tPLZ, tPHZ Output Disable Time, OE to Q VCC = 3.3 0.3 V RL = 1 kW VCC = 5.0 0.5V RL = 1 kW tOSLH, tOSHL Output to Output Skew VCC = 3.3 0.3 V (Note 1) VCC = 5.5 0.5 V (Note 1) CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Min Typ 7.3 9.8 4.9 6.4 7.0 9.5 5.0 6.5 7.3 9.8 5.5 7.0 9.5 6.5 Max 11.4 14.9 7.2 9.2 11.0 14.5 7.2 9.2 11.4 14.9 8.1 10.1 13.2 9.2 1.5 1.0 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 13.5 17.0 8.5 10.5 13.0 16.5 8.5 10.5 13.5 17.0 9.5 11.5 15.0 10.5 1.5 1.0 ns ns ns ns ns Unit ns
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MC74VHC373
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25C Symbol Cin Cout Parameter Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Test Conditions Min Typ 4 6 Max 10 TA = - 40 to 85C Min Max 10 Unit pF pF
Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Note 2) 27 pF
1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter Typ 0.6 - 0.6 Max 0.9 - 0.9 3.5 1.5 Unit V V V V
TIMING REQUIREMENTS (Input tr = tf = 3.0 ns)
TA = 25C Symbol tw(h) tsu th Parameter Minimum Pulse Width, LE Minimum Setup Time, D to LE Minimum Hold Time, D to LE Test Conditions VCC = 3.3 0.3 V VCC = 5.0 0.5 V VCC = 3.3 0.3 V VCC = 5.0 0.5 V VCC = 3.3 0.3 V VCC = 5.0 0.5 V Typ Limit 5.0 5.0 4.0 4.0 1.0 1.0 TA = - 40 to 85C Limit 5.0 5.0 4.0 4.0 1.0 1.0 Unit ns ns ns
ORDERING INFORMATION
Device MC74VHC373DWR2 MC74VHC373DWR2G MC74VHC373DTR2 MC74VHC373MEL MC74VHC373MELG Package SOIC-20 SOIC-20 (Pb-Free) TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 1000 Tape & Reel 1000 Tape & Reel 2500 Tape & Reel 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHC373
SWITCHING WAVEFORMS
tw LE 50% tPLH Q 50% VCC tPHL
D tPLH Q
50% tPHL 50% VCC
VCC GND
VCC GND
Figure 2.
Figure 3.
OE
50% tPZL Q 50% VCC tPZH Q 50% VCC tPHZ tPLZ
VCC GND HIGH IMPEDANCE VOL +0.3V VOL -0.3V HIGH IMPEDANCE LE D 50% tsu th 50% VALID
VCC GND VCC GND
Figure 4.
Figure 5.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6.
Figure 7.
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MC74VHC373
D0 3 D Q D1 4 D Q D2 7 D Q D3 8 D Q D4 13 D Q D5 14 D Q D6 17 D Q D7 18 D Q
LE LE 11
LE
LE
LE
LE
LE
LE
LE
OE
1 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7
Figure 8. EXPANDED LOGIC DIAGRAM
INPUT
Figure 9. INPUT EQUIVALENT CIRCUIT
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MC74VHC373
OUTLINE DIMENSIONS
SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B
20X
K REF
M
L
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
2X
L/2
20
11
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC74VHC373
OUTLINE DIMENSIONS
SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC74VHC373/D

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